| LDR | | 00000nam u2200205 4500 |
| 001 | | 000000431732 |
| 005 | | 20200224104544 |
| 008 | | 200131s2019 ||||||||||||||||| ||eng d |
| 020 | |
▼a 9781392318331 |
| 035 | |
▼a (MiAaPQ)AAI13917900 |
| 040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 247004 |
| 082 | 0 |
▼a 004 |
| 100 | 1 |
▼a Elyasi, Nima. |
| 245 | 10 |
▼a Extracting Better Performance from the Parallelism Offered by SSDS. |
| 260 | |
▼a [S.l.]:
▼b The Pennsylvania State University.,
▼c 2019. |
| 260 | 1 |
▼a Ann Arbor:
▼b ProQuest Dissertations & Theses,
▼c 2019. |
| 300 | |
▼a 123 p. |
| 500 | |
▼a Source: Dissertations Abstracts International, Volume: 80-12, Section: B. |
| 500 | |
▼a Publisher info.: Dissertation/Thesis. |
| 500 | |
▼a Advisor: Sivasubramaniam, Anand. |
| 502 | 1 |
▼a Thesis (Ph.D.)--The Pennsylvania State University, 2019. |
| 506 | |
▼a This item must not be added to any third party search indexes. |
| 506 | |
▼a This item must not be sold to any third party vendors. |
| 520 | |
▼a The majority of growth in the industry is driven by massive data processing which in turn is driving a tremendous need for high performance storage. To satisfy the lower latency demands, large-scale computing platforms have been making heavy use of flash-based Solid State Drives (SSDs), which provide substantially lower latencies compared to conventional hard disk drives. To satisfy the capacity and bandwidth demands, SSDs continue to scale by (i) adopting new flash technologies such as V-NAND, and (ii) embodying more flash chips which leads to higher levels of internal parallelism. With the tremendous growth in SSDs capacity and the continuing rise in their internal hardware parallelism, load imbalance and resource contention remain serious impediments towards boosting their performance. Employing and exploiting higher levels of internal parallelism in SSDs can even accentuate the load imbalance as variable-sized requests span more number of flash chips and impose more complexities to the request schedulers when coordinating the individual queues. On the other hand, the widely differential latency of the basic flash operations: read, write, and erase, exacerbates the load imbalance since not all chips are necessarily doing the same operation at the same time. As a consequence of such unbalanced system, SSD requests experience considerable inefficiencies in terms of non-uniformity and non-determinism in their service, which can in turn impair the profitability of client-facing applications. In this dissertation, remedies to alleviate these challenges are proposed, developed and evaluated. The proposed performance-enhancement mechanisms can be incorporated in the device firmware to provide faster and more consistent service.In this dissertation, we address the load imbalance problem by (i) exploiting the variation in the queue lengths to better take advantage of offered hardware parallelism while serving SSD requests, and (ii) balancing the load across different flash chips by opportunistically re-directing the load to less busy flash chips. First, we propose and develop a scheduling mechanism which orchestrates SSD requests at the (i) arrival time: when inserting requests in their respective queues, and (ii) service time: when issuing requests on flash chips. The former estimates and leverages the skews in completion of sub-requests in order to allow the new arrivals to jump ahead of the existing ones without affecting their response times. The latter, however, aims at achieving time sharing of available resources by coordinatedly scheduling sub-requests of each request at the service time. Such scheduling mechanisms are targeted at reducing the response time of SSD requests by coordinating SSD requests in their respective queues. Apart from such optimizations -which are restricted in terms of flash chips servicing a request, one can attempt to re-direct requests to other flash chips which are opportunistically free. Providing this re-direction opportunity is nontrivial for read requests. In the second part of this dissertation, we propose novel approaches to re-direct the load to less busy flash chips. With our proposed techniques, re-direction of read requests is achieved by (i) selective replication, wherein the value popularity is leveraged to replicate the popular data on multiple flash chips and provide more opportunities for read re-direction |
| 590 | |
▼a School code: 0176. |
| 650 | 4 |
▼a Computer Engineering. |
| 650 | 4 |
▼a Engineering. |
| 650 | 4 |
▼a Computer science. |
| 690 | |
▼a 0464 |
| 690 | |
▼a 0537 |
| 690 | |
▼a 0984 |
| 710 | 20 |
▼a The Pennsylvania State University.
▼b Computer Science and Engineering. |
| 773 | 0 |
▼t Dissertations Abstracts International
▼g 80-12B. |
| 773 | |
▼t Dissertation Abstract International |
| 790 | |
▼a 0176 |
| 791 | |
▼a Ph.D. |
| 792 | |
▼a 2019 |
| 793 | |
▼a English |
| 856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T15492597
▼n KERIS
▼z 이 자료의 원문은 한국교육학술정보원에서 제공합니다. |
| 980 | |
▼a 202002
▼f 2020 |
| 990 | |
▼a ***1008102 |
| 991 | |
▼a E-BOOK |