LDR | | 00000nam u2200205 4500 |
001 | | 000000431989 |
005 | | 20200224111954 |
008 | | 200131s2019 ||||||||||||||||| ||eng d |
020 | |
▼a 9781085688246 |
035 | |
▼a (MiAaPQ)AAI13903857 |
040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 247004 |
082 | 0 |
▼a 004 |
100 | 1 |
▼a Cota, Emilio Garcia. |
245 | 10 |
▼a Scalable Emulation of Heterogeneous Systems. |
260 | |
▼a [S.l.]:
▼b Columbia University.,
▼c 2019. |
260 | 1 |
▼a Ann Arbor:
▼b ProQuest Dissertations & Theses,
▼c 2019. |
300 | |
▼a 186 p. |
500 | |
▼a Source: Dissertations Abstracts International, Volume: 81-03, Section: B. |
500 | |
▼a Advisor: Carloni, Luca P. |
502 | 1 |
▼a Thesis (Ph.D.)--Columbia University, 2019. |
506 | |
▼a This item must not be sold to any third party vendors. |
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▼a The breakdown of Dennard's transistor scaling has driven computing systems toward application-specific accelerators, which can provide orders-of-magnitude improvements in performance and energy efficiency over general-purpose processors.To enable the radical departures from conventional approaches that heterogeneous systems entail, research infrastructure must be able to model processors, memory and accelerators, as well as system-level changes - such as operating system or instruction set architecture (ISA) innovations - that might be needed to realize the accelerators' potential. Unfortunately, existing simulation tools that can support such system-level research are limited by the lack of fast, scalable machine emulators to drive execution.To fill this need, in this dissertation we first present a novel machine emulator design based on dynamic binary translation that makes the following improvements over the state of the art: it scales on multicore hosts while remaining memory efficient, correctly handles cross-ISA differences in atomic instruction semantics, leverages the host floating point (FP) unit to speed up FP emulation without sacrificing correctness, and can be efficiently instrumented to - among other possible uses - drive the execution of a full-system, cross-ISA simulator with support for accelerators.We then demonstrate the utility of machine emulation for studying heterogeneous systems by leveraging it to make two additional contributions. First, we quantify the trade-offs in different coupling models for on-chip accelerators. Second, we present a technique to reuse the private memories of on-chip accelerators when they are otherwise inactive to expand the system's last-level cache, thereby reducing the opportunity cost of the accelerators' integration. |
590 | |
▼a School code: 0054. |
650 | 4 |
▼a Computer science. |
690 | |
▼a 0984 |
710 | 20 |
▼a Columbia University.
▼b Computer Science. |
773 | 0 |
▼t Dissertations Abstracts International
▼g 81-03B. |
773 | |
▼t Dissertation Abstract International |
790 | |
▼a 0054 |
791 | |
▼a Ph.D. |
792 | |
▼a 2019 |
793 | |
▼a English |
856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T15492490
▼n KERIS
▼z 이 자료의 원문은 한국교육학술정보원에서 제공합니다. |
980 | |
▼a 202002
▼f 2020 |
990 | |
▼a ***1008102 |
991 | |
▼a E-BOOK |