| LDR | | 00000nam u2200205 4500 |
| 001 | | 000000433166 |
| 005 | | 20200225112947 |
| 008 | | 200131s2019 ||||||||||||||||| ||eng d |
| 020 | |
▼a 9781085607391 |
| 035 | |
▼a (MiAaPQ)AAI13886716 |
| 040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 247004 |
| 082 | 0 |
▼a 621 |
| 100 | 1 |
▼a Almatouq, Munirah. |
| 245 | 10 |
▼a Performance and Power Optimization for Multi-core Systems Using Multi-level Scaling. |
| 260 | |
▼a [S.l.]:
▼b University of California, Irvine.,
▼c 2019. |
| 260 | 1 |
▼a Ann Arbor:
▼b ProQuest Dissertations & Theses,
▼c 2019. |
| 300 | |
▼a 87 p. |
| 500 | |
▼a Source: Dissertations Abstracts International, Volume: 81-02, Section: B. |
| 500 | |
▼a Advisor: Gaudiot, Jean-Luc. |
| 502 | 1 |
▼a Thesis (Ph.D.)--University of California, Irvine, 2019. |
| 506 | |
▼a This item must not be sold to any third party vendors. |
| 520 | |
▼a Integrating more cores per chip to increase the performance of processors has been trending for the past decade. However, this trend cannot be sustained because the reduction in power consumption per core has slowed down while the power budget per chip has not increased. Modern processor chips are becoming so power constrained to the point that not all their devices can be powered at once - this is often referred to as dark silicon. To maximize performance within these power constraints, the system must carefully select the set of resources to be used.To solve this problem, several power management techniques such as Dynamic Voltage/Frequency Scaling (DVFS), core scaling, and resource scaling have been the subject of active research and have proven to be effective. However, most of these solutions are sub-optimal because they explore only one layer of the architecture. Although considering one layer reduces the complexity of the technique, it limits the exploitation of potential improvement in performance and energy consumption.The problem is an order of magnitude more complex for power constrained multi-core architectures. We need power management systems that can take advantage of different scaling techniques. Many studies have been conducted on scaling with the sole objective of performance improvement. Nevertheless, few of them have considered both performance and energy consumption in the optimization process.This dissertation proposes an optimization technique that balances performance and energy consumption by applying a joint control of core, resource and frequency scaling. This system finds the optimal configuration for a given application and accordingly adapts the architecture configuration.The proposed technique consists of three stages: configuration sampling, response surface models to approximate performance and energy consumption, and online optimization using a genetic algorithm (GA). To evaluate the system, experiments were conducted on a simulated 12 core architecture. Our experiments have shown that the performance could improve by 15% on average while achieving energy savings of up to 26%. Using a per-core configuration improves the performance by 25% on average and reduces the energy by 18%. |
| 590 | |
▼a School code: 0030. |
| 650 | 4 |
▼a Computer engineering. |
| 690 | |
▼a 0464 |
| 710 | 20 |
▼a University of California, Irvine.
▼b Electrical and Computer Engineering - Ph.D.. |
| 773 | 0 |
▼t Dissertations Abstracts International
▼g 81-02B. |
| 773 | |
▼t Dissertation Abstract International |
| 790 | |
▼a 0030 |
| 791 | |
▼a Ph.D. |
| 792 | |
▼a 2019 |
| 793 | |
▼a English |
| 856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T15491528
▼n KERIS
▼z 이 자료의 원문은 한국교육학술정보원에서 제공합니다. |
| 980 | |
▼a 202002
▼f 2020 |
| 990 | |
▼a ***1816162 |
| 991 | |
▼a E-BOOK |