| LDR | | 00000nam u2200205 4500 |
| 001 | | 000000433996 |
| 005 | | 20200226135134 |
| 008 | | 200131s2019 ||||||||||||||||| ||eng d |
| 020 | |
▼a 9781085750011 |
| 035 | |
▼a (MiAaPQ)AAI22589787 |
| 040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 247004 |
| 082 | 0 |
▼a 004 |
| 100 | 1 |
▼a Dong, Xiaowan. |
| 245 | 10 |
▼a Toward Efficient and Protected Address Translation in Memory Management. |
| 260 | |
▼a [S.l.]:
▼b University of Rochester.,
▼c 2019. |
| 260 | 1 |
▼a Ann Arbor:
▼b ProQuest Dissertations & Theses,
▼c 2019. |
| 300 | |
▼a 225 p. |
| 500 | |
▼a Source: Dissertations Abstracts International, Volume: 81-03, Section: B. |
| 500 | |
▼a Advisor: Dwarkadas, Sandhya. |
| 502 | 1 |
▼a Thesis (Ph.D.)--University of Rochester, 2019. |
| 506 | |
▼a This item must not be sold to any third party vendors. |
| 520 | |
▼a Virtual memory is widely employed in most computer systems to make programming easy and provide isolation among different applications. Since virtual-to-physical address translation is on the critical path of every memory access, a lot of software and hardware techniques to reduce address translation overhead have been designed and implemented. However, memory management support on state-of-the-art architectures and operating systems encounters both performance and security challenges for today's applications and execution environments.From a performance perspective, both data and instruction working sets of modern applications are growing tremendously, resulting in the potential for high address translation overheads. While data address translation has received significant attention, instruction address translation performance has seen less attention at both architecture and operating system (OS) level. However, our performance analysis shows that a variety of services, ranging from compilers to web user-interface frameworks, which provide the infrastructure for many high-level applications, suffer from performance degradation due to instruction address translation overheads. Stall cycles due to instruction address translation account for up to 15% of the execution time. Moreover, instruction address translation overhead is likely to grow with the increasing degree of parallelism at both architecture and application levels. From a security perspective, attackers can leverage address translation information to steal confidential data via privileged side-channel attacks. Recent works such as Intel SGX and Virtual Ghost prevent OS kernels from reading or corrupting confidential application data. However, with the abilities to process page faults and configure page tables, a compromised OS can monitor the victim's memory access behavior and use this information to infer its secret data.In this dissertation, we show that (1) compaction and selective sharing of instruction address translation information can improve performance by reducing memory management overhead |
| 590 | |
▼a School code: 0188. |
| 650 | 4 |
▼a Computer science. |
| 690 | |
▼a 0984 |
| 710 | 20 |
▼a University of Rochester.
▼b Hajim School of Engineering and Applied Sciences. |
| 773 | 0 |
▼t Dissertations Abstracts International
▼g 81-03B. |
| 773 | |
▼t Dissertation Abstract International |
| 790 | |
▼a 0188 |
| 791 | |
▼a Ph.D. |
| 792 | |
▼a 2019 |
| 793 | |
▼a English |
| 856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T15493183
▼n KERIS
▼z 이 자료의 원문은 한국교육학술정보원에서 제공합니다. |
| 980 | |
▼a 202002
▼f 2020 |
| 990 | |
▼a ***1008102 |
| 991 | |
▼a E-BOOK |