| LDR | | 00000nam u2200205 4500 |
| 001 | | 000000434431 |
| 005 | | 20200226150754 |
| 008 | | 200131s2019 ||||||||||||||||| ||eng d |
| 020 | |
▼a 9781687927620 |
| 035 | |
▼a (MiAaPQ)AAI27536099 |
| 035 | |
▼a (MiAaPQ)umichrackham002335 |
| 040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 247004 |
| 082 | 0 |
▼a 621 |
| 100 | 1 |
▼a Aweke, Zelalem Birhanu. |
| 245 | 10 |
▼a Leveraging Processor Features for System Security. |
| 260 | |
▼a [S.l.]:
▼b University of Michigan.,
▼c 2019. |
| 260 | 1 |
▼a Ann Arbor:
▼b ProQuest Dissertations & Theses,
▼c 2019. |
| 300 | |
▼a 114 p. |
| 500 | |
▼a Source: Dissertations Abstracts International, Volume: 81-04, Section: B. |
| 500 | |
▼a Advisor: Austin, Todd M. |
| 502 | 1 |
▼a Thesis (Ph.D.)--University of Michigan, 2019. |
| 506 | |
▼a This item must not be sold to any third party vendors. |
| 506 | |
▼a This item must not be added to any third party search indexes. |
| 520 | |
▼a Errors in hardware and software lead to vulnerabilities that can be exploited by attackers. Proposed exploit mitigation techniques can be broadly categorized into two: software-only techniques and techniques that propose specialized hardware extensions. Software-only techniques can be implemented on existing hardware, but typically suffer from impractically high overheads. On the other hand, specialized hardware extensions, while improving performance, in practice require a long time to be incorporated into production hardware. In this dissertation, we propose adapting existing processor features to provide novel and low-overhead security solutions.In the first part of the dissertation, we show how modern hardware features can be used to provide efficient memory safety. One component of memory safety that has become important in recent years is temporal memory safety. Temporal memory safety techniques are used to detect memory errors such as use-after-free errors. This dissertation proposes a temporal memory safety technique that takes advantage of pointer authentication hardware to significantly reduce the memory and runtime overhead of traditional temporal safety techniques. Providing complete memory safety on resource constrained devices is expensive, therefore we propose software-based fault isolation (sandboxing) as an efficient alternative to constrain attackers' access to code and data in embedded systems. We show how we can use the memory protection unit (MPU) hardware available in many embedded devices along with a small trusted runtime to build a low-overhead sandboxing mechanism.In the second part of the dissertation, we show how hardware performance counters in modern processors can be used to detect rowhammer attacks. Our technique detects rowhammer attacks by monitoring for high locality memory accesses out of the last-level cache using hardware performance counters. The technique accurately detects rowhammer attacks with a low performance overhead and without requiring hardware modifications. |
| 590 | |
▼a School code: 0127. |
| 650 | 4 |
▼a Computer engineering. |
| 690 | |
▼a 0464 |
| 710 | 20 |
▼a University of Michigan.
▼b Computer Science & Engineering. |
| 773 | 0 |
▼t Dissertations Abstracts International
▼g 81-04B. |
| 773 | |
▼t Dissertation Abstract International |
| 790 | |
▼a 0127 |
| 791 | |
▼a Ph.D. |
| 792 | |
▼a 2019 |
| 793 | |
▼a English |
| 856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T15494186
▼n KERIS
▼z 이 자료의 원문은 한국교육학술정보원에서 제공합니다. |
| 980 | |
▼a 202002
▼f 2020 |
| 990 | |
▼a ***1008102 |
| 991 | |
▼a E-BOOK |