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020 ▼a 9781687999368
035 ▼a (MiAaPQ)AAI22624381
040 ▼a MiAaPQ ▼c MiAaPQ ▼d 247004
0820 ▼a 621
1001 ▼a Xiong, Qingqing.
24510 ▼a FPGA Acceleration of High Performance Computing Communication Middleware.
260 ▼a [S.l.]: ▼b Boston University., ▼c 2019.
260 1 ▼a Ann Arbor: ▼b ProQuest Dissertations & Theses, ▼c 2019.
300 ▼a 204 p.
500 ▼a Source: Dissertations Abstracts International, Volume: 81-04, Section: B.
500 ▼a Advisor: Herbordt, Martin C.
5021 ▼a Thesis (Ph.D.)--Boston University, 2019.
506 ▼a This item must not be sold to any third party vendors.
520 ▼a High-Performance Computing (HPC) necessarily requires computing with a large number of nodes. As computing technology progresses, internode communication becomes an ever more critical performance blocker. The execution time of software communication support is generally critical, often accounting for hundreds of times the latency of actual time-of-flight. This software support comes in two types. The first is support for core functions as defined in middleware such as the ubiquitous Message Passing Interface (MPI). Over the last decades this software overhead has been addressed through a number of advances such as eliminating data copies, improving drivers, and bypassing the operating system. However an essential core still remains, including message matching, data marshaling, and handling collective operations. The second type of communication support is for new services not inherently part of the middleware. The most prominent of these is compression
590 ▼a School code: 0017.
650 4 ▼a Computer engineering.
690 ▼a 0464
71020 ▼a Boston University. ▼b Electrical & Computer Engineering ENG.
7730 ▼t Dissertations Abstracts International ▼g 81-04B.
773 ▼t Dissertation Abstract International
790 ▼a 0017
791 ▼a Ph.D.
792 ▼a 2019
793 ▼a English
85640 ▼u http://www.riss.kr/pdu/ddodLink.do?id=T15494048 ▼n KERIS ▼z 이 자료의 원문은 한국교육학술정보원에서 제공합니다.
980 ▼a 202002 ▼f 2020
990 ▼a ***1008102
991 ▼a E-BOOK