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Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

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서명/저자사항Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs.
개인저자Sharma, Ankit.
단체저자명Purdue University. Electrical and Computer Engineering.
발행사항[S.l.]: Purdue University., 2018.
발행사항Ann Arbor: ProQuest Dissertations & Theses, 2018.
형태사항136 p.
기본자료 저록Dissertation Abstracts International 79-10B(E).
Dissertation Abstract International
ISBN9780438017320
학위논문주기Thesis (Ph.D.)--Purdue University, 2018.
일반주기 Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B.
Adviser: Kaushik Roy.
요약One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall en
요약Using full band quantum mechanical model within the Non-Equilibrium Green's Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy so
요약The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, an
일반주제명Electrical engineering.
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