자료유형 | 학위논문 |
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서명/저자사항 | Timing-Safe Hardware-Level Information Flow Control. |
개인저자 | Ferraiuolo, Andrew. |
단체저자명 | Cornell University. Electrical and Computer Engineering. |
발행사항 | [S.l.]: Cornell University., 2018. |
발행사항 | Ann Arbor: ProQuest Dissertations & Theses, 2018. |
형태사항 | 234 p. |
기본자료 저록 | Dissertation Abstracts International 79-10B(E). Dissertation Abstract International |
ISBN | 9780438027244 |
학위논문주기 | Thesis (Ph.D.)--Cornell University, 2018. |
일반주기 |
Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B.
Adviser: Edward Suh. |
요약 | Developing secure processors has become increasingly important. Recent advancements in commercial security architectures such as Intel SGX have garnered much attention. The promise of these architectures is compelling |
요약 | Information flow security is a promising approach for verifying hardware systems. Information flow tracks and constrains the movement of data throughout a system ensuring that confidentiality and integrity are not violated. Information flow cont |
요약 | This thesis enables future hardware designs to provide strong assurance through information flow control. This is achieved through two major thrusts of research: 1) developing a practical, expressive hardware description language for enforcing i |
일반주제명 | Computer engineering. Computer science. |
언어 | 영어 |
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