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Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs
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| 자료유형 | 학위논문 |
|---|---|
| 서명/저자사항 | Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs. |
| 개인저자 | Sharma, Ankit. |
| 단체저자명 | Purdue University. Electrical and Computer Engineering. |
| 발행사항 | [S.l.]: Purdue University., 2018. |
| 발행사항 | Ann Arbor: ProQuest Dissertations & Theses, 2018. |
| 형태사항 | 136 p. |
| 기본자료 저록 | Dissertation Abstracts International 79-10B(E). Dissertation Abstract International |
| ISBN | 9780438017320 |
| 학위논문주기 | Thesis (Ph.D.)--Purdue University, 2018. |
| 일반주기 |
Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B.
Adviser: Kaushik Roy. |
| 요약 | One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall en |
| 요약 | Using full band quantum mechanical model within the Non-Equilibrium Green's Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy so |
| 요약 | The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, an |
| 일반주제명 | Electrical engineering. |
| 언어 | 영어 |
| 바로가기 | 
: 이 자료의 원문은 한국교육학술정보원에서 제공합니다. |
