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Performance Analysis of Timing-Speculative Processors
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| 자료유형 | 학위논문 |
|---|---|
| 서명/저자사항 | Performance Analysis of Timing-Speculative Processors. |
| 개인저자 | Assare, Omid. |
| 단체저자명 | University of California, San Diego. Computer Science and Engineering. |
| 발행사항 | [S.l.]: University of California, San Diego., 2019. |
| 발행사항 | Ann Arbor: ProQuest Dissertations & Theses, 2019. |
| 형태사항 | 140 p. |
| 기본자료 저록 | Dissertations Abstracts International 81-02B. Dissertation Abstract International |
| ISBN | 9781085656849 |
| 학위논문주기 | Thesis (Ph.D.)--University of California, San Diego, 2019. |
| 일반주기 |
Source: Dissertations Abstracts International, Volume: 81-02, Section: B.
Advisor: Gupta, Rajesh. |
| 이용제한사항 | This item must not be sold to any third party vendors. |
| 요약 | Timing guardbands act as a barrier protecting conventional processors from circuit-level phenomena like timing errors. Timing-speculative (TS) processors replace these guardbands with timing error detection and recovery circuits to guarantee correct execution. For timing speculation to be effective, the performance and/or energy improvements gained from eliminating the guardbands must outweigh the costs of detecting and recovering from timing errors. The high costs and limited benefits that have been an obstacle to adoption of timing speculation in commercial designs have been steadily improving over the past decade. Likewise, recent advances in design of ultra-fast on-chip voltage regulators and all-digital phase locked loops with sub-nanosecond response times have increased the potential benefits by enabling more aggressive timing speculation schemes.This dissertation is motivated by another contributing factor limiting broader adoption of TS processors---complexity of their performance analysis. The absence of timing guardbands complicates timing analysis of TS processors as circuit and architecture, and their interdependence, must be considered simultaneously. We present a cross-layer performance analysis framework for TS processors that spans the system stack from circuit to application, including dynamic timing analysis tools at the level of gates, microarchitecture, and architecture, an instruction-level timing error model, and a statistical program error rate estimation methodology. We then use our framework to study the performance of a TS processor with an emphasis on characterizing the role of software. Our experiments show that the combination of running application and its input data can change the performance of a TS processor by as much as 25 percent, demonstrating that application-specific analysis is necessary for accurate evaluation of TS processors and should be used to inform design decisions and assess the suitability of applications for timing speculation.Performance of TS processors also relies on accurate prediction of the optimal operating point. Our experiments show that, in a typical case, the most commonly used policy achieves only a fraction of the potential gains of timing speculation. Inspired by our modeling of timing errors, the improved timing speculation strategies we propose in this dissertation can realize a more than 50 percent throughput improvement compared to a guardbanded design. |
| 일반주제명 | Computer engineering. Computer science. Electrical engineering. |
| 언어 | 영어 |
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: 이 자료의 원문은 한국교육학술정보원에서 제공합니다. |
