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Ultra-low Leakage, Energy-efficient Digital Integrated Circuit and System Design
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| 자료유형 | 학위논문 |
|---|---|
| 서명/저자사항 | Ultra-low Leakage, Energy-efficient Digital Integrated Circuit and System Design. |
| 개인저자 | da Silva Cerqueira, Joao Pedro . |
| 단체저자명 | Columbia University. Electrical Engineering. |
| 발행사항 | [S.l.]: Columbia University., 2019. |
| 발행사항 | Ann Arbor: ProQuest Dissertations & Theses, 2019. |
| 형태사항 | 141 p. |
| 기본자료 저록 | Dissertations Abstracts International 81-06B. Dissertation Abstract International |
| ISBN | 9781392341834 |
| 학위논문주기 | Thesis (Ph.D.)--Columbia University, 2019. |
| 일반주기 |
Source: Dissertations Abstracts International, Volume: 81-06, Section: B.
Advisor: Seok, Mingoo. |
| 이용제한사항 | This item must not be sold to any third party vendors. |
| 요약 | The advances of the complementary metal-oxide-semiconductor (CMOS) technology manufacturing and design over the years have enabled a diverse range of applications across the power consumption, performance, and area (PPA) spectra. Many of the recent and prospective applications rely on the availability of energy-autonomous, miniaturized systems, i.e., ultra-low power (ULP) VLSI systems, which are generally characterized by extreme resource limitations. Some examples of applications are wireless sensing platforms, body-area sensor networks (BASN), biomedical and implantable devices, wearables, hearables, and monitors. Within the context of such applications, the key requirements are long lifetime and miniaturized size (sub-/millimeter-scale). In order to enable both requirements, energy-efficiency is the key metric. It allows for extended battery lifetime and operation with the energy that can be harvested from the environment, and it limits the size (volume) of the energy sources utilized to power these systems.Ultra-low voltage (ULV) operation is a key technique in which the VDD of circuits is reduced from nominal to near or below the threshold voltage of the transistor. It is a powerful knob that has been largely exploited by designers in order to achieve ultra-low power consumption and high energy-efficiency in CMOS. Existing ULP VLSI systems typically operate at a lower supply voltage thereby reducing their energy consumption by one to two orders of magnitude in order to enable the aforementioned applications.While supply voltage scaling is a promising measure for achieving low power and reducing energy consumption, it brings up several challenges. One critical issue is the leakage energy dissipated by the devices, which is magnified in portion to the total energy consumption at ULV. The reason is that, as VDD scales from nominal to near-threshold and sub-threshold, transistors become increasingly slower and they accumulate more leakage (i.e., static) power over longer cycle times. This energy waste accounts for a significant portion of the system's total energy consumption, offsets the gains provided by voltage scaling, defines the minimum energy per operation, and poses a practical limit for the system's energy-efficiency.This thesis presents selected research works on ultra-low leakage, energy-efficient digital integrated circuit design. More specifically, it describes novel and key techniques for minimizing the energy waste of idle/underutilized and always-on hardware. The main goal of such techniques is to push the envelope of energy-efficiency in energy-autonomous, miniaturized VLSI systems. Such techniques are applied to key building blocks of emerging mobile and embedded computing devices resulting in state-of-the-art energy-efficiencies. |
| 일반주제명 | Electrical engineering. Computer engineering. Computer science. |
| 언어 | 영어 |
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