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Scalable Emulation of Heterogeneous Systems
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| 자료유형 | 학위논문 |
|---|---|
| 서명/저자사항 | Scalable Emulation of Heterogeneous Systems. |
| 개인저자 | Cota, Emilio Garcia. |
| 단체저자명 | Columbia University. Computer Science. |
| 발행사항 | [S.l.]: Columbia University., 2019. |
| 발행사항 | Ann Arbor: ProQuest Dissertations & Theses, 2019. |
| 형태사항 | 186 p. |
| 기본자료 저록 | Dissertations Abstracts International 81-03B. Dissertation Abstract International |
| ISBN | 9781085688246 |
| 학위논문주기 | Thesis (Ph.D.)--Columbia University, 2019. |
| 일반주기 |
Source: Dissertations Abstracts International, Volume: 81-03, Section: B.
Advisor: Carloni, Luca P. |
| 이용제한사항 | This item must not be sold to any third party vendors. |
| 요약 | The breakdown of Dennard's transistor scaling has driven computing systems toward application-specific accelerators, which can provide orders-of-magnitude improvements in performance and energy efficiency over general-purpose processors.To enable the radical departures from conventional approaches that heterogeneous systems entail, research infrastructure must be able to model processors, memory and accelerators, as well as system-level changes - such as operating system or instruction set architecture (ISA) innovations - that might be needed to realize the accelerators' potential. Unfortunately, existing simulation tools that can support such system-level research are limited by the lack of fast, scalable machine emulators to drive execution.To fill this need, in this dissertation we first present a novel machine emulator design based on dynamic binary translation that makes the following improvements over the state of the art: it scales on multicore hosts while remaining memory efficient, correctly handles cross-ISA differences in atomic instruction semantics, leverages the host floating point (FP) unit to speed up FP emulation without sacrificing correctness, and can be efficiently instrumented to - among other possible uses - drive the execution of a full-system, cross-ISA simulator with support for accelerators.We then demonstrate the utility of machine emulation for studying heterogeneous systems by leveraging it to make two additional contributions. First, we quantify the trade-offs in different coupling models for on-chip accelerators. Second, we present a technique to reuse the private memories of on-chip accelerators when they are otherwise inactive to expand the system's last-level cache, thereby reducing the opportunity cost of the accelerators' integration. |
| 일반주제명 | Computer science. |
| 언어 | 영어 |
| 바로가기 | 
: 이 자료의 원문은 한국교육학술정보원에서 제공합니다. |
